Trying to preserve other peoples code
The article discusses a command-line application that generates Verilog or VHDL code for CRC calculations. It provides detailed instructions on how to build and use the tool, including examples of polynomial string representations. The tool aims to preserve the original code and is credited to its creator, Evgeni Stavinov.
- ▪The CRC Generator can handle data widths and polynomial widths between 1 and 1024.
- ▪It is a cross-platform compatible tool written in C.
- ▪The application was originally available interactively on the OutputLogic website.
Opening excerpt (first ~120 words) tap to expand
CRC Generator for Verilog or VHDL Description CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible. Build To build on linux using gcc: g++ -o crc_gen crc_gen.cpp Usage Invoke the tool via command line: ./crc_gen [language] [data_width] [poly_width] [poly_string] Options: language: verilog or vhdl data_width: data bus width ${1..1024}$ poly_width: polynomial width ${1..1024}$ poly_string: a string that describes CRC polynomial, eg: Ethernet MAC FCS uses poly 04C11DB7 Notes on poly_string Examples: $05 = x^5+x^2+1$ $8005 = x^{16} + x^{15}+ x^2+ 1$ The string representation (0x05, 0x8005) doesn’t include highest degree…
Excerpt limited to ~120 words for fair-use compliance. The full article is at GitHub.