Rolled Silicon 3D Chips Could Shrink Circuits
Researchers at the University of Illinois Urbana-Champaign have developed a method for creating rolled silicon 3D chips using nanoscale membranes. This innovation allows circuits to stretch across three layers of silicon, potentially leading to more compact and efficient semiconductor designs. The work focuses on junctionless transistors, which could pave the way for advanced 3D chip integration.
- ▪The new method utilizes roll-on nanoscale membranes to create 3D chips.
- ▪This technology enables circuits to span across three layers of silicon.
- ▪The research highlights the potential of junctionless transistors in semiconductor design.
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SemiconductorsNewsComputing Junctionless Transistors Show a New Path to 3D Chips Roll-on nanoscale membranes make circuits that stretch across three layers of siliconCharles Q. Choi27 May 20265 min readCharles Q. Choi is a contributing editor for IEEE Spectrum.Hyunjun Nam [left] and Yung Man Yu, in the lab of Qing Cao at the University of Illinois Urbana-Champaign, reflect on their work. Fred Zwicky {"customDimensions": {"5":"Charles Q. Choi","11":2676931596,"7":"3d-chips, junctionless-transistors, 3d-integration","10":"3d-chips","6":"semiconductors","8":"05/27/2026"}, "post": {"id": 2676931596, "providerId": 20, "sections": [497728257, 539621009, 544169523, 2267926519, 539617903, 2289611742, 2295022037, 2289605432], "authors": [21075163], "tags": ["3d-chips", "junctionless-transistors",…
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