IBM MCGA Gate Array Reverse Engineering
IBM's MCGA (Multi-Color Graphics Array) was a low‑cost video chipset used in the PS/2 Model 25 and Model 30 computers. The chipset comprises a memory controller gate array (72X8300) and a video formatter gate array (72X8205), both of which have been reverse engineered using Seiko SLA‑type gate arrays. The reverse‑engineering revealed undocumented register functions, genlock capabilities, and detailed cell layouts of the chips.
- ▪The MCGA chipset includes a memory controller gate array (72X8300) that implements an MC6845 sync generator and manages video RAM and ISA bus interfaces.
- ▪The video formatter gate array (72X8205) decodes ISA addresses, handles the RAMDAC, and generates pixel data for graphics and text modes.
- ▪Reverse engineering showed the 72X8300 uses a Seiko SLA6430 gate array with 4,342 basic cells, while the 72X8205 uses a Seiko SLA6330 gate array with 3,312 basic cells.
- ▪Undocumented register bits enable genlock to external HSYNC/VSYNC signals and provide manufacturing test modes that affect clock selection and counter speedup.
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IBM MCGA Gate Array Reverse Engineering IBM's MCGA (Multi-Color Graphics Array) is a low-cost video chipset introduced with the PS/2 models 25 and 30. The Epson Equity 1e uses MCGA compatible video but does not use the same chips. The IBM chipset consists of the memory controller gate array and the video formatter gate array. Some examples of these were fabricated on an internal IBM gate array process, while others used an external gate array part by Seiko. Memory Controller Gate Array (72X8300) This gate array contains an implementation of the MC6845 sync generator IC, manages the video RAM interface to the ISA bus, manages the character RAM interface, and a few other miscellaneous functions including clock selection and monitor ID readback.
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Excerpt limited to ~120 words for fair-use compliance. The full article is at GitHub.